The present invention relates to a method of manufacturing a semiconductor device, and particularly to a technique which is effective when applied to a method of manufacturing a semiconductor device having an inspection pattern for inspecting mask misalignment in a lithographic step for ion implantation.
The manufacturing process of a semiconductor device includes a plurality of lithographic steps to process a conductor film or an insulating film into an intended shape or to form a mask layer for use in ion-implanting an impurity into a semiconductor substrate or the like. In each of the lithographic steps, using, e.g., a reduced projection exposure method or the like, a mask pattern formed over a mask or reticle (hereinafter generally referred to as a mask) is transferred onto a photoresist layer formed over the semiconductor substrate. In the transfer step, an alignment mark pattern formed over the semiconductor substrate is detected and a mask is aligned (positioned) with respect to the alignment mark pattern, and then exposure treatment is performed. Then, development treatment and baking treatment are performed on the photoresist layer subjected to the exposure treatment to complete a photoresist mask having a pattern equal to the mask pattern. Then, using the photoresist mask, a conductor film, an insulating film, or the like is processed or impurity ions are implanted.
However, in the formation of the photoresist mask, mask misalignment with respect to an underlying layer formed in the semiconductor substrate occurs. Accordingly, using the photoresist layer used to form the photoresist mask, an inspection pattern is simultaneously formed, and an amount of misalignment of the inspection pattern with respect to an alignment target layer (alignment target mark) formed of the underlying layer is measured.
Japanese Unexamined Patent Publication No. 2005-150251 (Patent Document 1) relates to an improvement in alignment mark portion (mark pattern mentioned above).
Japanese Unexamined Patent Publication No. 2000-292905 (Patent Document 2) relates to improvements in mark pattern and misalignment inspection pattern.